1 module nxt.cpuid_ex;
2 
3 version(none)
4 {
5 /**
6    See_Also: http://blog.melkerlitsgard.se/2016/05/12/cache-sizes-with-cpuid/
7 */
8     int getCacheSize(int cacheLevel)
9     {
10         // Intel stores it's cache information in eax4, with ecx as index
11         // The information received is as following:
12         // ebx[31:22] = Ways of associativity
13         // ebx[21:12] = Physical line partitions
14         // ebx[11: 0] = Line size
15         int[4] cpuInfo = 0;
16         asm
17         {
18             mov EAX, functionID;
19             mov ECX, cacheLevl; // The index here is the cache level (0 = L1i, 1 = L1d, 2 = L2 etc.)
20             cpuid;
21             mov cpuInfo, EAX;
22             mov cpuInfo + 4, EBX;
23             mov cpuInfo + 8, ECX;
24             mov cpuInfo + 12, EDX;
25         }
26         int ways = cpuInfo[1] & 0xffc00000; // This receives bit 22 to 31 from the ebx register
27         ways >>= 22; // Bitshift it 22 bits to get the real value, since we started reading from bit 22
28         int partitions = cpuInfo[1] & 0x7fe00; // This receives bit 12 to 22
29         partitions >>= 12; // Same here, bitshift 12 bits
30         int lineSize = cpuInfo[1] & 0x7ff; // This receives bit 0 to 11
31         int sets = cpuInfo[2]; // The sets are the value of the ecx register
32         // All of these values needs one appended to them to get the real value
33         return (ways + 1) * (partitions + 1) * (lineSize + 1) * (sets + 1);
34     }
35 }